1. Field of the Invention
The present invention relates to a method and arrangement of coherently demodulating PSK (Phase Shift Keying) signals, and more specifically to such a method and arrangement via which an incoming multi-phase-modulated signal can effectively be reproduced irrespective of a large amount of carrier frequency deviations and via which proper operations can be assured under low C/N (carrier to noise ratio) environments. The present invention is well suited for use in a mobile communications system by way of example.
2. Description of the Prior Art
As is known in the art, coherent (viz., synchronous) demodulation is to detect baseband signals through multiplication of incoming modulated IF (Intermediate Frequency) signals by a reproduced carrier signal.
Before turning to the present invention it is deemed preferable to discuss a prior art technique with reference to FIGS. 1 and 2. FIG. 1 is a block diagram showing a conventional coherent demodulator which is generally depicted by reference numeral 10. FIG. 2 is a block diagram illustrating in detail a single-tuned filter of FIG. 1.
In FIG. 1, a m-phase phase-modulated analog IF signal Vin is applied to two mixers 12, 14 (m is a positive integer such as 2, 4, 8, 16, . . . ). The incoming signal Vin is given by ##EQU1## where p, q indicate respectively modulating signals, Wc an angular frequency of a carrier signal, and e.sup.j(Wot+.theta.o) the carrier signal.
The mixer 12 is coupled to a local oscillator 16 while the other mixer 14 is coupled, via a .pi./2 phase shifter 18, to the oscillator 16. A local signal Vo generated from the blocks 16, 18 is given by ##EQU2## In more specific terms, if the output of the local oscillator 16 is cos (Wot+.theta.o) then the output of the phase shifter 18 is sin (Wot+.theta.o) or vice versa. The output of the mixers 12, 14 (denoted by Vmix) is written by ##EQU3## where * indicates a conjugate complex number, and EQU Wr=Wc-Wo EQU .theta.r=.theta.c-.theta.o
Low-pass filters (LPFs) 20, 22 are provided to remove the second term of the right side of equation (3). Thus, analog-to-digital (A/D) converters 24, 26 produce the following signal Vad. EQU Vad=(p+jq)e.sup.j(Wrt+.theta.r) ( 4)
A timing circuit 28 is provided to apply timing clocks (CLKs) to a plurality of digital blocks which follow the low-pass filters 20, 22. The application of timing clocks to digital blocks, however, is not shown merely for the sake of simplifying drawings.
The output Vad of the A/D converters 24, 26 is applied, via channel filters (viz. matched filters) 30 and 32, to delay circuits 34, 36 and also to a multiplier (viz., power-of-m circuit) 38.
The multiplier 38 multiplies the output Vad by itself m times and generates a signal denoted by Vad.sup.m. ##EQU4##
The multiplier 38 applies the output thereof to a single-tuned filter 40 which, as shown in FIG. 2, includes an adder 42, a constant value generator 44, a multiplier 46 and a delay circuit 48. The constant value generator 44 issues a real value denoted by .alpha., while the delay circuit 48 retards the output of the adder 42 by one sampling time period.
The transfer function of the filter 40 is written by EQU T(Z)=1/(1-.alpha.Z.sup.-1) (6)
where Z=e.sup.ST (S is a differential operator, and T a sampling period).
If the sampling frequency is sufficiently high, equation (6) can be approximated as follows. EQU T(S)={1/(1=.alpha.)}/(1+S.tau.) (7)
where .tau.=.alpha.T/(1-.alpha.)
Thus, the output of the filter 40, denoted by Vt, is given by ##EQU5## Accordingly, the frequency error Wr causes the following problems.
(a) The amplitude of Vt is lowered and thus C/N is reduced; and
(b) Phase drift represented by tan.sup.-1 mWrt is undesirably induced.
Merely for the convenience of simplifying the discussion, it is assumed that the value of .alpha.r is sufficiently small.
A divider 50 divides the received signal by itself m times and, generates the output (denoted by Vrc) which is a reproduced carrier and written by EQU Vrc=Vt.sup.1/m =e.sup.j{(Wrt+.theta.r)-tan.spsp.-1.sup.Wr.tau.}
Following this, the reproduced carrier Vrc is multiplied by Vad at the multiplier 52 (FIG. 1). Thus, the modulating signals p, q are reproduced at the output of the multiplier 52. The output of the multiplier 52 (denoted by Vdm) is given by ##EQU6## It is understood that in order to accurately reproduce the modulating signals p and q, the frequency difference Wrt should be rendered zero.
As mentioned above, merely one filter (viz., filter 40) is provided in the conventional coherent demodulator 10 and, accordingly it is extremely difficult to properly determine or design the pass-band of the filter 40. That is, if the pass-band of the filter 40 is narrowed to increase a signal-to-noise ratio (S/N) for complying with low C/N environments, it may fail to transfer the received signal therethrough if the frequency difference Wr.tau. exhibits a large amount of value. Conversely, if the pass-band is extended or widened, another problem is caused which undesirably lowers S/N. Further, if a large amount of frequency deviation occurs in the carrier, the prior art may be unable to implement the coherent detection using such a single filter.